Information processing system including multiple function translators

ABSTRACT

An information processing system characterized by modularity of design and good maintenance features includes a plurality of oneout-of-N translators each of which includes double-output detection circuitry. Some of the translators are operated in a conventional manner to convert a multidigit input word into energization of one particular one of N output lines emanating therefrom. Others of the translators are supplied with periodic clock signals, steady-state reference signals and instruction signals. In response to such a set of signals, these other translators are operated in a unique manner to provide a specified plurality of sequential control signals which are applied to a matrix array to cause the readout therefrom of a corresponding plurality of stored words.

United States Patent Primary Examiner-Paul Jv Henon AssistantExaminer-Mark Edward Nusbaum Altorneys-Ri .I. Guenther and Kenneth B.Hamlin ABSTRACT: An information processing system characterized bymodularity of design and good maintenance features includes a pluralityof one-out-of-N translators each of which includes double-outputdetection circuitry. Some of the translators are operated in aconventional manner to convert a multidigit input word into energizationof one particular one of N output lines emanating therefrom. Others ofthe translators are supplied with periodic clock signals, steady-statereference signals and instruction signals. In response to such a set ofsignals, these other translators are operated in a unique manner toprovide a specified plurality of sequential control signals which areapplied to a matrix array to cause the readout therefrom of acorresponding plurality of stored words.

DAYA AND LOGIC CIRCUITS |72| Inventor Wing N. To

Glen Ellyn, III. [2!] Appl No 735,297 [22] Filed June 7. I968 [45]Patented July 20. I97! I 73] Assignee BeII TeIephone Laboratories,Incorporated Murray Hill, Berkeley Heights. NJ.

[54] INFORMATION PROCESSING SYSTEM INCLUDING MULTIPLE FUNCTIONTRANSLATORS ll Claims, [0 Drawing Figs.

[52] US. Cl. 340M725, 1791i 8, 340/347 [51] InLCI. G06f5/00 [$0]Fieldolseareh H 340/1725, 347; l79/l8 [56] References Cited UNITEDSTATES PATENTS 3,229,275 I/l966 Warman et al. l. 340/347 3,235,6642/l966 Muroga el al..., 340/347 3,344,410 9/1967 Collins etaI i.340/1725 on uAs1sl-- CON ROL :09 ClRCU L CO1 e 599 2 N. V 598:? m iota 5mmsti o 7 nficligfi M 4 i TO MASTER CONT.

ccr

ERRoR CONTROL CIRCUIT TRAN SLATOR 209 *R ff 2|3 FIG. 28

INHIBIT\ Y PRETRANSLATOR FIG. 2/1

FROM

M M F Y PRETRANSLATOR 234 FROM [238.

ATENTED JUL20|97I FROM CLOCK CCT. I08

INSTR. DECODER FROM DATA 8. LOGIC CCTS. I22

m M OmmRw TIADHI MA I. w w u m 2 NU 2 Q mmC 2 II I l. W IL rW ii \L; 5T1 W H O D. S 1 m R c I 5 m M R B 4 2 2 2 MM 2 I, I \l 4 6 a m 2 2 K I ICm W N no 0 TI L 5 L 5 MS AT C N N C U IE A AC MC 0 RR 0 0mm MO FT C RCOC F. M RE R 06 FD p R0 X FL CROSSPOINT PATENTEU JUL 2 0 19?:

SHEEI 3 BF 8 Y PRETRANSLATOR FIG. 2C

W TO CROSS POI NTS FROM CLOCK CIRCUIT I06 VERTICAL/Q u NES CROSSPOINTSHORIZONTAL LINES x PRETRANsLAmR 7' ATENTEnJuIzoIsrI 3,594,730

SHEET u 0F 8 FIG. 25

CLOCK SIGNAL FROM CCT, I08 MW OUTPUT OF INSTRUCTION l I DECODER I02OUTPUT OF CROSSPOINT 206 00 0Q .00..Q I...... 20202030202020.

OUTPUT OF CROSSPOINT 207 OUTPUT OF INSTRUCTION l DECODER I02 OUTPUT OFCROSSPOINT 208 t t t t t6 TIME PATENTEDJUL20I97I 3594730 sum 5 0F 8 FIG.2F

CLOCK SIGNAL FROM CCT, I08 m OUTPUT OF INSTRUCTION I I DECODER I02 TOCROSSPOINTS 2IO AND 2II OUTPUTS OF DATA AND I LOGIC CCTS I22 TOCROSSPOINTS 2I2 AND 2I3| OUTPUT OF CROSSPOINT 2IO TIME LJUU

CLOCK SIGNAL I I I I CLOCK SIGNAL 7 0 2 F F EG 0 O OTI T Tm T R W UUE P0P0 DIRD TD: TDI WN C ONE 0 0 D R R C C I I OUTPUT OF I CROSSPOINT 20aOUTPUT OF CROSSPOINT 209 I I INHIBIT L SIGNALS TIME PATENTED JUL20 I971SHEET 7 OF 8 FIG. 4

CLOCK SIGNAL CLOCK SIGNAL LOCK GNAL INSTRUCTION SIGNAL J OUTPUT OFCROSSPOINT 206 OUTPUT OF CROSSPOINT 207 OUTPUT 0F CROSSPOINT 208 OUTPUTOF CROSSPOINT 209 OUTPUT 0F CROSSPOINT 260 OUTPUT OF CROSSPOINT 26IOUTPUT OF CROSSPOINT 262 A M a, TI M E OUTPUT 0F CROSSPOINT 263 PATENTEDJULZUIQTI 3 594 73 SHEET 8 0F 8 FIGS OUTPUT OF TRANSLATOR H4 CLOCKSIGNAL TO TRANSLATOR H5 OUTPUT OF TRANSLATOR H5 CHECK TIME FORTRANSLATOR H5 CLOCK SIGNAL TO TRANSLATOR H6 OUTPUT OF TRANSLATOR ||6CHECK TIME FOR TRANSLATOR H6 INFORMATION PROCESSING SYSTEM INCLUDINGMULTIPLE FUNCTION TRANSLATORS This invention relates to the processingof information signals and more particularly to an informationprocessing system that includes multiple-function translators.

BACKGROUND OF THE INVENTION In recent years considerable effort has beendirected to the task of designing electronic systems in integratedcircuit form. The advantages of integrating such systems on a largescale basis are well known. These advantages include considerations ofcost, space, speed and power dissipation.

The advantages of large-scale integration of a complex system can besignificantly enhanced if the number of different basic constituentcircuits out of which the system is formed can be kept to a relativelylow figure. In addition, the efi'iciency and reliability of such anintegrated system can be greatly increased if effective troubledetection techniques can be easily embodied therein.

SUMMARY OF THE INVENTION An object of the present invention is animproved information processing system.

More specifically, an object of this invention is an informationprocessing system having a relatively few basic constituent circuits.

Another object of the present invention is an improved and simplifiedinformation processing system adapted to be implemented in integratedcircuit form and characterized by modularity of design and goodmaintenance features.

Briefly, these and other objects of the present invention are realizedin a specific illustrative system embodiment thereof that comprises aplurality of one-out-of-N translators of the type disclosed in mycopending application, Ser. No. 45 7,406, filed May 20, 1965, now U.S.Pat. No. 3,428,945, issued Feb. I8, 1969. Each such translator includesassociated error-detection circuitry and is therefore equipped to imparterrorcontrol capabilities to the overall system. In addition, inaccordance with the principles of this invention, clock signals areapplied to such a translator to cause it to generate any desired numberof sequential control signals. Furthermore, in the illustrative system,such translators are adapted to perform logic operations.

An entire information processing system can be constructed byinterconnecting a plurality of identically configured (but differentlyoperated one-out-of-N translators with a small number of other differenttypes of basic components. When implemented in integrated circuit form,the resultant system exhibits an advantageous simplicity and modularityof design.

A feature of the present invention is that a one-out-of-N translatorhaving error-control capabilities is driven in a unique way by clocksignals to generate a plurality of sequential control signals.

Another feature of this invention is that such a translator is driven byclock signals to provide one of several control signal sequencesdepending respectively on which one of several sets of enabling signalsis applied to the translator.

A further feature of the present invention is that such translators areoperated in an overall system to provide a check both on the occurrenceof double outputs therefrom and on the presence of certain clock signalsintended to be applied thereto.

BRIEF DESCRIPTION OF THE DRAWING A complete understanding of the presentinvention and of the above and other features, variations and advantagesthereof may be gained from a consideration of the following detaileddescription of an illustrative embodiment thereof presented hereinbelowin conjunction with the accompanying drawing, in which:

FIG. I is a block diagram of an information processing system made inaccordance with the principles of the present invention;

FIG. 2A shows a one-out-of-N translator of the type included in the FIG.I system;

FIG. 28 illustrates the configuration of a crosspoint unit included inthe translator of FIG. 2A;

FIGS. 2C and 2D respectively depict the arrangement of the Y and Xpretranslators included in the FIG. 2A translator; and

FIGS. 25, 2F and 3 through 5 depict various waveforms that are helpfulin understanding the mode of operation of the vanous arrangements shownin the drawing.

DETAILED DESCRIPTION The specific illustrative information processingsystem shown in FIG. I constitutes a general-purpose stored programprocessor. In the depicted system, digital words representative ofinstructions to be decoded and executed are contained in a program storeI00 which, for example, may be of the type described in "No. l ESSProgram Store" by C. F. Ault et al., pages 2097-2146, The Bell SystemTechnical Journa1(hereinafter BSTJ), Part I, Sept. I964. In aconventional and well understood manner, selected ones of theseinstructions are applied one at a time from the store to an instructiondecoder I02 via a buffer register I04. (The instruction decoder I02 maycomprise a binary to one-out-of-N translator of the type described inthis application. In addition, the register I04 is a conventional bufferunit which may be of the type described on page 2073 ofNo. 1 BS5 LogicCircuits and Their Application to the Design of the Central Control(hereinafter "Logic Circuits) by W. B. Cagle et BSTJ, Part I, Sept.I964. The selection of and sequencing through the instructions containedin the store I00 is controlled by a master control circuit 106 that iscoupled to the store I00. The circuit I06 also controls the operation ofa clock circuit 100 which is adapted to apply clock or timing signalsvia a bus 109 to various indicated ones of a plurality of one-out-of-Ntranslators 110 through I16. The master control circuit I06 and theclock circuit 108 may be constructed in accordance with the descriptioncontained on pages 1908-1920 (see FIG. 35 in particular) of0rganizationof the No. l ESS Central Processor" by J. A. Harr et al., BSTJ, Part I,Sept. 1964 and on pages 20552095 of the aforecited Logic Circuits.Herein for illustrative purposes each of these translators will beassumed to be a one-out-of-32 translator of the type shown in FIG. 3A ofthe above-identified copending application. (This type of translatorwill be described in detail below.) In such a translator each differentone of 32 possible 5-digit binary input words is effective to select adifferent one of 32 output lines extending from the translator.

The system of FIG. I also includes a standard coordinate matrix arrayI20 which includes a multiplicity of horizontal input lines and aplurality, for example l5, vertical output lines. Illustratively, thearray includes a transistor crosspoint unit positioned at preselectedones of the intersections formed by the aforementioned horizontal andvertical lines. Accordingly, energization of a particular one of thehorizontal input lines is effective to cause a unique l5-digit word toappear in parallel on the output lines. It is apparent, therefore, thatthe array 120 functions as a converter in which energization of aparticular horizontal input line causes a corresponding IS-digit outputword to be read out therefrom. Alternatively, the array 120 may be ofthe diode type described in U.S. Pat. No. 3,245,05], issued Apr. 5, 1966to J. H. Robb, or of the type described in U.S. Pat. No. 3,383,663,issued May I4, I968toC.A.M.David.

Additionally, the FIG. I system includes conventional data and logiccircuits (represented by block 122) which respond to variouscombinations of control signals from the translators I14 through 116 toperform therein various prescribed data manipulation and logicoperations. One particular illustrative data manipulation operation thatthe circuits I22 are adapted to perform in response to output signalsfrom the translators 114 through I16 involves (I) transferring data froma first designated register to a bus, (2) clearing a second designatedregister, and (3) then transferring the data from the bus to the secondregister. (The first and second registers and the data bus are assumedto be contained within the block I22.) Alternatively, the unit 122 mayinclude plural processors whose sequence of operation is to becontrolled in accordance with output signals from the translators I14through H6.

in actual operation the instruction decoder I02 of FIG. I responds to aninstruction word applied thereto from the register I04 to energize aspecified one of a multiplicity of output lines I25 emanating therefrom.Some of these output lines (represented by bus I27) extend directly torespective inputs of the matrix array I20. If one of these directlyextending output lines is selected by the decoder 102, a resultantIS-digit word uniquely representative thereof is applied from the array120 to the translators I14 through II6.

Some of the instructions decoded by the unit I02 specify in effect aplurality of sequential operations and therefore require for theirexecution that a series of control signals be applied to the matrixarray I20. Each instruction of this type can be considered to designatea series of so-called microoperations. Decoding of each suchplural-operation instruc tion results in the selection of one of theoutput lines I25 that does not extend directly to the array 120.Instead, in accordance with the principles of the present invention,such lines are connected to the array I via the translators III] through113. Additionally, decoding of such an fllstruction results in thedecoder 102 signaling the master control circuit I06 to trigger thecircuit I08 to apply specified clock signals to the translators IIOthrough I13. In response to such clock signals and instruction signalsfrom the decoder I02, a particular one of the translators 110 throughI13 is operated to generate a sequence of 2, 4, 8 or more controlsignals which are applied to respective input lines of the array 120 tocause a readout therefrom of a corresponding number of IS-digit outputwords. In this way energization of a single output line emanating fromthe decoder I02 is converted or expanded into a plurality ofoperation-controlling outputs from the matrix array I20.

As a basis for understanding the particular unique manner in which thetranslators depicted in FIG. I are operated, reference is made to theillustrative translator configuration shown in FIG. 2A. The translator200 shown therein includes Y and X pretranslators 202 and 204 whoseparticular arrangements will be described below in connection with FIGS.2C and 2D. Four vertical output lines emanate from the Y pretranslator202 and eight horizontal output lines extend from the X pretranslator204. These leads intersect to form a coordinate matrix having 32intersections at each of which is connected a cross-point unit. The fourcross-points 206 through 209 in the topmost row of the matrix arerepresented by X and 0 symbols, as are the four cross-points 260 through263 included in the second row and the four cross-points 210 through 213included in the last row.

Advantageously, the output leads of the X-designated crosspoint unitsshown in FIG. 2A extend to the respective inputs of one 0R circuit (notshown) included in an error control circuit 215, and the output leads ofthe O-designated cross-points extend to a second 0R circuit (not shown)in the circuit 215. Illustratively, the overall arrangement of thecircuit 215 corresponds to that of the error detecting circuit 300 andits associated indicator 385 shown in FIG. 3A of the above-citedapplication. In particular, the above-specified 0R circuits correspond,for example, to the circuits 375 and 380 of FIG. 3A. Thus, if eachcross-point unit of a set including at least one 0- designatcd unit andone X-decignated unit simultaneously pro vide output selection signals,the circuit 2I5 will indicate by a signal an output lead 216 that amalfunction (double-output condition) has occurred.

Each of the crowpoint units included in the translator of FIG. 2A may,for example, comprise a logic circuit of the type shown in FIG. 2B. Thiscircuit, which is a conventional NAND gate, is adapted to provide arelatively high positive potential on output lead 220 if at least one ofthe signals applied to the cathodes of input diodes 221 through 225thereof is a relatively low near-ground potential. On the other hand, ifall of the input signals comprise relatively high positive potentials,the u ut signal of the depicted cross-point is a near-ground potential.Herein a cross-point will be considered to have been selected if thepotential of its output lead is relatively low.

As shown in FIG. 2B, the inputs to the illustrated crosspoint unit(which may, for example, be considered to cor respond to the cross-point210 of FIG. 2A) are derived from the Y and X pretranslators 202 and 204,the instruction decoder 102 and the data and logic circuits 122. Theoutput lead of the specified cross-point unit is connected to the errorcontrol circuit 215 and the matrix array 120.

In addition, another input line 226 is shown in FIG. 2B. As specifiedlater hereinbelow in connection with the description of the translatorsI15 and H6, clock signals applied to this line from the circuit I08 maybe utilized to sequentially enable a plurality of translators.

FIGS. 2C and 2D respectively show illustrative implementations for the Yand X pretranslators 202 and 204 of FIG. 2A. As specified in myaforecited copending application, these pretranslator: are normallyadapted to respond to a S-digit input word to select a particularindicated one of a plurality of associated cross-point units.

Each of the logic symbols employed in FIGS. 2C and 2D represents a NANDcircuit such as that depicted in FIG. 2B. In order not to undulycomplicate the showings of FIGS. 2C and 2D, various interconnectionstherein have not actually been drawn in, but instead have been clearlyindicated by labeling the leads that are shown. It is to be understoodthat correspondingly designated leads in those figures are in factintended to be electrically connected together.

The mode of operation of the FIG. 2A translator is providing, forexample, two sequential control signals in response to a singleinstruction signal from the decoder 102 and appropriate clock signalsfrom the circuit 108 can be understood from a consideration of FIGS. 2Aand 2E. (For such operation the four leads shown in FIG. 2A extendinginto the left end of the Y pretranslator 202 need not be connected toany circuitry external to the translator. Alternatively, these leads maybe extended to the clock circuit I08 wherein relatively high positivepotentials are respectively applied thereto.) Assume that the clockcircuit 108 applies ground signals to the input leads 230 and 232 of thetranslator of FIG. 2A and, in addition, applies a clock signal (whosewaveform is shown in the first row of FIG. 2E) to the input line 234thereof. Furthermore, assume that the instruction decoder 102respectively supplies the signals shown in the second and fifth rows ofFIG. 2E to the input leads 236 and 238 of the FIG. 2A translator. (It isnoted that selection of a particular one of the output leads emanatingfrom the decoder 102 is manifested by the presence of a relatively highpotential thereon.)

In response to the application of the abov; pecified signals to thetranslator of FIG. 2A, there appears on each of the horizontal linesemanating from the X pretranslator 204 a relatively high potentialsignal. (This may be easily verified by tracing through theconfiguration of FIG. 2D.) Similarly, it is apparent that the signalsappearing on the four vertical lines emanating from the Y pretranslator202 of FIG. 2A are respectively from left to right: high, low, high andlow. Moreover, the instruction signals (from the decoder 102)respectively applied to the crossfpoint units 206 through 209 of FIG. 2Aduring the time interval designated 1, through i, in FIG. 2F are high,high, low and low. Hence, it is evident that only the crnss'point unit206 has no low signal applied thereto. As a result, only the cross-pointunit 206 provides a relatively low output signal during the specifiedtime interval. This out put signal (croxs'hatched for cmphaxix) ixindicated in the third row of FIG. 2B.

Subsequently, during the time interval 1, through r (FIG. 2E) the fourvertical lines shown in FIG. 2A have, from left to right, low, high, lowand high potentials respectively applied thereto by the Y pretranslator202. And, since only the crosspoint unit 207 of the set 207 and 209 hasa high instruction signal applied thereto during the interval t, through1,, only the unit 207 provides a relatively low output signal (seefourth row of FIG. 2B) during that interval.

During the time interval designated 1, through I in FIG. 25 anotherinstruction signal (shown in the fifth row thereof) plus the periodicclock signal shown in the first row plus the aforementioned groundcondition are applied to the illustrative translator shown in FIG. 2A.As a consequence thereof, the translator provides at the outputs of thecross-point units 208 and 209 the cross-hatched relatively low signalsrepresented in the sixth and seventh rows of FIG. 2E.

Thus, it has been shown that the application of a periodic clock signaland a steady-state ground signal, together with a single instructionsignal from the decoder 102, is effective to provide at the output ofthe FIG. 2A translator two sequential control signals during theexistence of each single instruction signal. In turn, these controlsignals are applied to different input lines of the matrix array 120(FIG. 1) to cause two digit words to be read out of the array 120 insequence.

The output lines emanating from the cross-point units 206 through 209 ofFIG. 2A are also connected to the error control circuit 215. Hence, theundesired simultaneous occurrence of relatively low outputs from 0 andX-designated cross-point units is detected by the circuit 215. Anappropriate indication thereof appears on the line 216 which may, forexample, extend to the master control circuit 106 of FIG. 1. In turn,the circuit 106 may energize an alarm or otherwise signal the occurrenceof an error in the system.

At time 1, (FIG. 2B) the output of the cross-point unit 206 undergoes atransition from a low to a high value, and the output of the unit 207goes from high to low. To eliminate the possibility that the errorcontrol circuit 215 will provide a false error detection during thesetransitions, it is advantageous to inhibit the operation of the circuit215 during an interval that extends slightly before and after 1,. Asimilar inhibiting action is advantageously arranged to occur about ISuch inhibiting signals, supplied by the clock circuit 108 under controlof the master circuit 106, are represented in the last row of FIG. 25.

The translator 200 shown in FIG. 2A is also adapted to perform logicoperations under the control of conditional signals applied thereto fromthe data and logic circuits 122 of FIG. 1. By way of illustration, thebottom four cross-point units 210 through 213 of the translator 200 arearranged to carry out this type of operation. Specifically, in this modeof operation the two pairs of cross-points comprising the units 210-211,and 212-213, are respectively supplied with complementary signals fromthe circuits 122. At the same time, an instruction signal from thedecoder 102 is applied via a lead 240 to all the units 210 through 213.In addition, as before, ground signals are applied to the leads 230 and232, and a clock signal of the form shown in the first row of FIG. 2F isapplied to the lead 234. More specifically, an instruction signal (shownin the second row of FIG. 2F) is applied to the lead 240. Moreover, thesignal represented in the third row of FIG. 2F is applied from thecircuits 122 to the cross-points 210 and 211, and the signal shown inthe fourth row thereof is applied from the circuits 122 to thecross-points 212 and 213. As a result of these particular inputconditions, the cross-points 210 and 211 are controlled to provide twosequential control signals during the time interval in which the notedinstruction signal is maintained at its relatively positive level. Thesecontrol signals are represented in the fifth and sixth rows of FIG. 2F.During this time interval neither one of the cross-points 212 and 213provides a relatively low output signal because of the low signal(fourth row of FIG. 2F) applied thereto from the circuits 122v Theconditional operation described above can easily be modified to causethe cross-points 212 and 213 to provide the two above-mentionedsequential control signals and to block the cross-points 210 and 211from providing such signals. This modified operation is achieved simplyby interchanging the signals indicated in the third and fourth rows ofFIG. 2F.

The various output signals provided by the cross-points 210 through 213are applied to the matrix array 120 to serve as row selection signalstherefor. These output signals are also applied to the error controlcircuit 215 wherein a check for double outputs is carried out. To ensureagainst false doubleoutput indications, it is advantageous, as before,to apply an inhibit signal (see last row of FIG. 2F) to the circuit 215during a time period in which both cross-point output signals areundergoing transitions.

In accordance with the principles of the present invention thetranslator 200 shown in FIG. 2A is also capable of being operated toprovide four or more sequential control signals during the occurrence ofa single positive instruction signal. FIGS. 3 and 4 represent twoillustrative modes of operation in which the translator 200 respectivelyprovides four and eight sequential control signals.

The operation represented in FIG. 3 is realized by (l) (2) groundsignals to the leads 230 and 232 of the translator 200, (2) applying theclock signal shown in the first row of FIG. 3 to the lead 234, (3)applying the clock signal shown in the second row of FIG. 3 to the inputleads 250 and 252 of the Y pretranslator 202 (which leads and theirspecific manner of interconnection with the NAND gates in thepretranslator 202 are depicted in FIG. 2C), (4) applying the clocksignal shown in the third row of FIG. 3 to the Y pretranslator inputleads 254 and 256 (shown in FIGS. 2A and 2C), and (S) applying theinstruction signal shown in the fourth row of FIG. 3 to each of thecross-points 206 through 209 (via the leads 236 and 238).

The operation represented in FIG. 4 is achieved in the following manner:l) ground signals are applied to the lead 230 (FIG. 2A) that extends tothe Y pretranslator 202 and also to the leads 272 through 275 (FIG. 2D)that extend to the X pretranslator 204, (2) the clock signal shown inthe first row of FIG. 4 is applied to the lead 234 of FIG. 2A, (3) theclock signal shown in the second row of FIG. 4 is applied to the leads250 and 252 (FIG. 2C), (4) the clock signal shown in the third row ofFIG. 4 is applied to the leads 254 and 256 (FIG. 2C), (5) the clocksignal shown in the fourth row of FIG. 4 is applied to the lead 271 ofFIG. (6) (6) lead 270 is not connected to any signal source(alternatively, this lead may be connected to a relatively highpotential source), and (7) the instruction signal shown in the fifth rowof FIG. 4 is applied via a lead (not shown) to each of the cross-points206 through 209 and 260 through 263.

In response to the various signals specified in the paragraphimmediately above, the translator 200 of FIG. 2A is operated to provideeight sequential control signals, as depicted in the sixth throughthirteenth rows of FIG. 4. In this way a single instruction signal fromthe decoder 102 is converted or expanded into eight row selectionsignals for the matrix array 120.

In view of the disclosure above and in accordance with the principles ofthe present invention, other sets of clock signals to be applied to aoneout-ofN translator to cause it to generate any desired number ofsequential control signals may easily be devised.

For ease of discussion and so as not to unduly expand the number offigures included in the drawing, the translator of FIG. 2A has beenconsidered herein as being capable of operating to provide 2, 4 or 8sequential control signals. Such operation is entirely feasible.However, in one specific illustrative information processing system madein accordance with the principles of the present invention, eachdifferent one of the translators through 113 shown in FIG. 1 isadvantageously adapted to provide only one specified number ofsequential output signals. Thus, for example, the translator 110 isoperated to provide two sequential control signals, the translator 111provides four such signals, the translator 112 generates eight suchsignals, and so forth.

In carrying out data manipulation operations in the illustrative FIG. 1system, it may be necessary to ensure that the signals read out of thematrix array 120 are gated through the translators 114 through 116 in aspecified order. Thus, for example, in carrying out the above-mentionedfirst register-tobus-to-second register manipulation, the operation ofclearing the second register must be carried out before the data on thebus is gated to the second register. lllustratively, the necessarysequential control action may be achieved by applying timing or enablingsignals to the translators 115 and "6 from the clock circuit 108 vialeads 280 and 282. The nature of these enabling signals and of othersignals employed to carry out the specified data manipulation operationoperation is shown in FIG. 5.

Assume that the translator "4 (FIG. 1) is controlled by a 5- digitoutput word from the array 120 to provide a relatively low potentialsignal (first row of HO. 5) on one of the leads extending between thetranslator [l4 and the circuits 122. This signal is provided during thetime interval designated 1, through i, in FIG. 5. (ln carrying out thisconversion operation, the translator 114 operates in the conventionalmanner for which it was originally designed, which manner is describedin detail in the aforementioned copending application.) In response tothis signal from the translator 114, data is transferred from a firstregister in the block 122 to a data bus therein. During the initialportion of this interval (i.e., in the interval 1, through I lowpotential input clock signals are applied to each of the cross-points inthe translators I and "6 (for example via the lead 226 shown in FIG. 28)to hold all the outputs of the cross-points at their relatively highlevels. These clock signals are represented in the second and fifth rowsof FIG. 5 and the corresponding conditions of the translators 11S and[16 (in the interval I, through t,) are respectively depictedthereunder.

Subsequently, in the interval designated I, through I, in FIG. 5, anenabling clock signal (shown in the second row of FIG. 5) is applied tothe translator 115 whereby an output signal (third row) is then providedon a selected one of the output leads thereof. Similarly, a later clocksignal in the interval I, through I, is effective to enable thetranslator H6 and to allow it to provide an output signal (sixth row) ona particular lead thereof that is determined by the nature of the inputsignals from the matrix array 120.

The error control circuitry included in each of the translators 114through 116 is effective to check for the occurrence of erroneous doubleoutputs from those translators. Such error information is applied, forexample, to the master control circuit 106. In addition, the errorcontrol circuitry is advantageously utilized to periodically checkwhether or not the format of the above-described sequential enabling orclock signals applied to the translators 115 and 116 is correct. This isdone by monitoring the aforementioned OR gates included in the errorcontrol circuitry of the translators.

More specifically, during the time interval designated I, through I. inFIG. 5, the OR gates in the error control circuitry included in thetranslators 114 and 115 are monitored by the master control circuit 106.This monitoring or checking interval is represented in the fourth row ofFIG. 5. If the clock signal applied to the translator 115 is low (as itshould be) during this interval, only the translator [14 will besupplying an output signal to the circuits 122. If, however, due to somemalfunction in the system, the potential of the clock signal applied tothe translator 115 is relatively high during the interval I, through Iboth of the translators 1H and 115 will provide output signals duringthe noted checking interval. Such a double-output indication will bedetected by the circuit 106. It is advantageous to choose the checkinterval to be I, through r. to avoid the possibility of overlap withthe output of the translator 115 occurring during the interval 1,through r,.

Similarly, during the interval 1, through r, indicated in FIG. 5,another checking operation takes place. This operation is effective todetermine whether or not the translators I N and "6 are providingsimultaneous output signals.

Thus, in accordance with the principles of the present invention therehas been described herein an information processing system that includesmultiple-function translators. By applying various clock and enablingsignals to the translators, and by selectively monitoring their outputconditions during prescribed intervals, it has been shown that thetranslators can be operated in a unique manner to provide sequentialcontrol signals and, in addition, that the output status of a singletranslator or of several translators can easily be checked fordouble-output occurrences. Due to the inclusion of thesemultiple-function translators, the resultant system is characterized bymodularity of design and good maintenance features.

It is to be understood that the above-described arrange ments are onlyillustrative of the application of the principles of the presentinvention. In accordance with these principles numerous otherarrangements may be devised by those skilled in the art withoutdeparting from the spirit and scope of the invention.

What I claim is:

1. In combination in an information processing system,

a plurality of one-out-of-N translators each including a plurality ofoutput lines,

means for applying successive instruction signals to said translators,and

means for applying periodic clock signals and steady-state referencesignals to said translators,

each of said translators including means responsive to said appliedsignals for generating and respectively applying to specified ones ofthe output lines thereof a plurality of sequential control signalsduring the time in which a single instruction signal of said successiveinstruction signals is applied to the translator.

2. A combination as in claim I further including a matrix arrayconnected to said output lines to provide a multidigit output word fromthe array in response to each control signal applied thereto.

3. A combination as in claim 2 wherein each of said translators includeserror control circuitry for detecting the generation by said translatorof simultaneous control signals.

4. A combination as in claim 3 further including an additional pluralityof one-out-of-N translators each including a plurality of output lines,each of said additional translators being responsive to a portion ofeach output word provided by said matrix array for applying a controlsignal to one of the output lines thereof.

5. A combination as in claim 4 further including means for sequentiallyenabling selected ones of the additional plurality of translators.

6. A combination as in claim 5 further including data and logic circuitsconnected to the output lines of said additional plurality oftranslators.

7. A combination as in claim 6 further including means for applying toat least one of said first-mentioned plurality of translatorsconditional signals indicative of information representations containedin said data and logic circuits.

8. A multiple function translator comprising a plurality of cross-pointunits,

means responsive to an input binary code word for selecting a particularone of said units,

means for applying steady-state signals and timing signals to saidselecting means, and

means for applying each of successive instruction signals simultaneouslyto respective selected sets of plural units whereby the respective unitsof each set in turn are controlled to provide sequential output signalsin response to each different one of said successively appliedinstruction signals.

9. In combination in a translator,

first and second pretranslators each including a plurality of linesemanating therefrom, each of the lines from said first pretranslatorbeing disposed in an orthogonal relationship with respect to each of thelines from said second ones of said cross-point units.

[0. A combination as in claim 9 further including means for applyingconditional logic signals directly to said selected cross-point units.

11. A combination as in claim [0 further including error controlcircuitry connected to said cross-point units for detecting theoccurrence ofdouble outputs therefrom

1. In combination in an information processing system, a plurality ofone-out-of-N translators each including a plurality of output lines,means for applying successive instruction signals to said translators,and means for applying periodic clock signals and steady-state referencesignals to said translators, each of said translators including meansresponsive to said applied signals for generating and respectivelyapplying to specified ones of the output lines thereof a plurality ofsequential control signals during the time in which a single instructionsignal of said successive instruction signals is applied to thetranslator.
 2. A combination as in claim 1 further including a matrixarray connected to said output lines to provide a multidigit output wordfrom the array in response to each control signal applied thereto.
 3. Acombination as in claim 2 wherein each of said translators includeserror control circuitry for detecting the generation by said translatorof simultaneous control signals.
 4. A combination as in claim 3 furtherincluding an additional plurality of one-out-of-N translators eachincluding a plurality of output lines, each of said additionaltranslators being responsive to a portion of each output word providedby said matrix array for applying a control signal to one of the outputlines thereof.
 5. A combination as in claim 4 further including meansfor sequentially enabling selected ones of the additional plurality oftranslators.
 6. A combination as in claim 5 further including data andlogic circuits connected to the output lines of said additionalplurality of translators.
 7. A combination as in claim 6 furtherincluding means for applying to at least one of said first-mentionedplurality of translators conditional signals indicative of informationrepresentations contained in said data and logic circuits.
 8. A multiplefunction translator comprising a plurality of cross-point units, meansresponsive to an input binary code word for selecting a particular oneof said units, means for applying steady-state signals and timingsignals to said selecting means, and means for applying each ofsuccessive instruction signals simultaneously to respective selectedsets of plural units whereby the respective units of each set in turnare controlled to provide sequential output signals in response to eachdifferent one of said successively applied instruction signals.
 9. Incombination in a translator, first and second pretranslators eachincluding a plurality of lines emanating therefrom, each of the linesfrom said first pretranslator being disposed in an orthogonalrelationship with respect to each of the lines from said secondpretranslator thereby to define a multiplicity of intersections, amultiplicity of cross-point units respectively connected to the linesdefining each of said intersections, means for applyiNg periodic clockand steady-state reference signals to said first and secondpretranslators, and means for applying instruction signals directly toselected ones of said cross-point units.
 10. A combination as in claim 9further including means for applying conditional logic signals directlyto said selected cross-point units.
 11. A combination as in claim 10further including error control circuitry connected to said cross-pointunits for detecting the occurrence of double outputs therefrom.